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3D IC & TSV Profiles (report & database)

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Advanced Packaging - 3D IC profile of company

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Price

2990 

Publication date

 September 2007

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The report provides more than 300 slides "ready to use" for your own business. IDMs and OSATs players have been investigated. For each profile, you will have access to the following features:

  • Company overview: 
    - Financial highlights 
    - Company products and markets 
    - Strategic alliances & partnerships

  • Mapping of the R&D labs and main manufacturing fabs locations:  Key R&D, Front-end, Back-end, and Assembly site activities have been identified

  • Key contacts developing the TSV technology

  • Summary of the 3D IC technologies developed

  • Latest announcements

  • Product Roadmaps

Product objectives
A unique tool for equipment & material suppliers to develop their business worldwide with the key players of the 3D IC industrial value chain.
A complete company profiles report to enable suppliers of semiconductor industry to detect new opportunities on the 3D Packaging semiconductor market. 

Product overview
This
unique report & database will provide you a global picture of what is happening today in the 3D IC world: gain access quickly to the profiles of the Top 50 key players developing the TSV "Through Silicon Via" technology, including locations (R&D labs, cutting edge pilot lines and manufacturing plants), key business & technical contacts, product roadmaps, 3D processes developed, strategic alliances & partnerships. The covered geographical areas includes North America, Europe and Asia.

Key features
Whiling to develop your business
and learn more about the key 3D IC players? Our report and  database are 2 unique tools to answer your questions:

Application fields covered:

  • RF-SiP: Integrated passives, antennas, amplifiers, MMICs, power components...

  • CMOS imagers: Chip scale Opto WLP and 3D LSI CMOS image sensors

  •  Memories: NAND Flash, NOR Flash and DRAMs

  •  3D MEMS: Silicon Microphones, pressure sensors, inertial sensors and MOEMS to be stacked on CMOS wafers

  • Memories & logic: FPGAs, SRAM / DRAM cache memories to be stacked directly onto microprocessor cores

Elements included:
·
 Comprehensive Database:
à 3D IC segmentation incorporated
à Customized research enabled
à Easy to share & extract information

    · Complete Profiles Report:
à Top 50 players covered
à 3D technologies developed
à Latest product achievements
à Key Contacts & Locations   
à Companies Roadmaps to production

Facts & Figures
For each
player in the database, you will gets its:
 
· Activities through our 3D IC segmentation:
          
- RF-SiP, Flash, DRAM, CIS, Logic, MEMS, IP, R&D supply

 
· Key contacts:
          
- Business, Engineering and Researcher contacts
 · Fabs identity & locations:
- Creation date, generic coordinates, clean room class &  size, fab capacity, wafer size, product lines developed

 
· 3D technologies developed:
-
Stacking scheme: C2C, C2W, W2W, number of stacked layers
 
- Bonding technology: Cu-to-Cu, adhesive, direct oxide, eutectic? 
-
Wafer level: substrate material, wafer thickness budget, handling process developed
 - Via level: holes diameters, interconnect densities, drilling technologies (wet etch, laser, DRIE...)  and filling processes (Copper,  Tungsten, Poly-silicon...)

 

 


Yole Développement: 45 rue Sainte Geneviève, F-69006 Lyon, France.  TEL: (33) 472 83 01 80   FAX: (33) 472 83 01 83   E-Mail: info @yole.fr